A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

    研究成果: Article査読

    52 被引用数 (Scopus)

    抄録

    A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-μm CMOS technology. The receiver active area is 0.8 mm2 and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 μm × 85 μzm and 13.2 mW for the equalizer, and 145 μm × 80 μm and 10 mW for the ISI monitor.

    本文言語English
    ページ(範囲)986-993
    ページ数8
    ジャーナルIEEE Journal of Solid-State Circuits
    40
    4
    DOI
    出版ステータスPublished - 2005 4

    ASJC Scopus subject areas

    • 電子工学および電気工学

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