A 100-Gb-Ethernet subsystem for next-generation metro-area network

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi

研究成果: Conference article査読

4 被引用数 (Scopus)


An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks. A parallel link of 12 10-Gb/s synchronized parallel optical lanes is proposed. The 10 optical lanes are used to transmit 10-bit parallel data. The one of redundant lanes transmits a forward error correction code ((132b, 140b) Hamming code) to achieve highly-reliable (BER < 10-12) data transmission, and the other lane transmits a parity data used for the fault-lane recovery. Here, a 64B/66B code-sequence-based de-skewing mechanism is proposed, and its effectiveness to realize low-latency compensation of the inter-lane skew (< 80 ns) is shown. We have implemented the 100-Gb-Ethernet interface architectures into FPGA circuits, and confirmed the performance of 100 Gb/s data communication with compact 385-kgates circuit size, which is practically small for implementation in a single LSI circuit.

ジャーナルIEEE International Conference on Communications
出版ステータスPublished - 2005 9月 15
イベント2005 IEEE International Conference on Communications, ICC 2005 - Seoul, Korea, Republic of
継続期間: 2005 5月 162005 5月 20

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学


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