A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda

A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

研究成果: Paper › 査読

抄録

This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.

本文言語	English
ページ	202-205
ページ数	4
出版ステータス	Published - 2004 9月 29
イベント	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States 継続期間: 2004 6月 17 → 2004 6月 19

Other

Other	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
国/地域	United States
City	Honolulu, HI
Period	04/6/17 → 04/6/19

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

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title = "A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS",

abstract = "This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.",

keywords = "CDR, CMOS, Equalizer, ISI, Receiver",

author = "Yasumoto Tomita and Masaya Kibune and Junji Ogawa and Walker, {William W.} and Hirotaka Tamura and Tadahiro Kuroda",

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AU - Tomita, Yasumoto

AU - Kibune, Masaya

AU - Ogawa, Junji

AU - Walker, William W.

AU - Tamura, Hirotaka

AU - Kuroda, Tadahiro

PY - 2004/9/29

Y1 - 2004/9/29

N2 - This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.

AB - This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.

KW - CDR

KW - CMOS

KW - Equalizer

KW - ISI

KW - Receiver

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T2 - 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI

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A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

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ASJC Scopus subject areas

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