This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.
|出版ステータス||Published - 2004 9月 29|
|イベント||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States|
継続期間: 2004 6月 17 → 2004 6月 19
|Other||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI|
|Period||04/6/17 → 04/6/19|
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