A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications

Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A small gate count 8 bit bidirectional phase domain MAC (PMAC) circuit is proposed for DNN inference applications targeting IoT edge. PMAC consumes significantly smaller power than standard fully digital MACs, owing to its efficient analog accumulation nature based on Gated-Ring-Oscillator (GRO). Compared with the previous first PoC of PMAC, the bidirectional architecture proposed in this paper achieves 20% less gate count, which is comparable with fully digital MACs, and relaxes system design constraints by eliminating phase error originating in leakage current. Asynchronous readout technique and 2-step DTC for the better system throughput and compact implementation, respectively, are presented for the first time. The PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

本文言語English
ホスト出版物のタイトル2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1-4
ページ数4
ISBN(電子版)9781538664124
DOI
出版ステータスPublished - 2018 12 14
外部発表はい
イベント2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China
継続期間: 2018 11 52018 11 7

出版物シリーズ

名前2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
国/地域Taiwan, Province of China
CityTainan
Period18/11/518/11/7

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル