A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link

Kaoru Kohira, Hiroki Ishikuro

研究成果: Article査読

2 被引用数 (Scopus)

抄録

This paper introduces low-power and small area injectionlocking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2-V supply at 12.5 Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87 ps. The CDR area is 0.165 mm2.

本文言語English
ページ(範囲)458-465
ページ数8
ジャーナルIEICE Transactions on Electronics
E99C
4
DOI
出版ステータスPublished - 2016 4月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル