A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Yuki Urano, Won Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.

    本文言語English
    ホスト出版物のタイトル2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    ページ1576-1579
    ページ数4
    DOI
    出版ステータスPublished - 2013 9 9
    イベント2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
    継続期間: 2013 5 192013 5 23

    出版物シリーズ

    名前Proceedings - IEEE International Symposium on Circuits and Systems
    ISSN(印刷版)0271-4310

    Other

    Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    国/地域China
    CityBeijing
    Period13/5/1913/5/23

    ASJC Scopus subject areas

    • 電子工学および電気工学

    フィンガープリント

    「A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル