A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

研究成果: Conference contribution

81 引用 (Scopus)

抜粋

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

元の言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者L.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
47
出版物ステータスPublished - 2004
イベントDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
継続期間: 2003 2 152003 2 19

Other

OtherDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference
United States
San Francisco, CA.
期間03/2/1503/2/19

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

これを引用

Mizoguchi, D., Yusof, Y. B., Miura, N., Sakurai, T., & Kuroda, T. (2004). A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS). : L. C. Fujino, M. Amiri, A. Grabel, D. Jaeger, & K. C. Smith (版), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (巻 47)