A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

    研究成果: Conference article

    81 引用 (Scopus)

    抜粋

    A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

    元の言語English
    ページ(範囲)142-143+131+517
    ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    47
    出版物ステータスPublished - 2004 6 2
    イベントDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
    継続期間: 2003 2 152003 2 19

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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