A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration

Koki Tanaka, Ryo Saito, Hiroki Ishikuro

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.

本文言語English
ホスト出版物のタイトルESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
編集者Franz Dielacher, Wolfgang Pribyl, Gernot Hueber
出版社IEEE Computer Society
ページ327-330
ページ数4
ISBN(電子版)9781467374705
DOI
出版ステータスPublished - 2015 10 30
イベント41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
継続期間: 2015 9 142015 9 18

出版物シリーズ

名前European Solid-State Circuits Conference
2015-October
ISSN(印刷版)1930-8833

Other

Other41st European Solid-State Circuits Conference, ESSCIRC 2015
国/地域Austria
CityGraz
Period15/9/1415/9/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル