A 1Tb/s 3W inductive-coupling transceiver chip

Noriyuki Miura, Tadahiro Kuroda

    研究成果: Conference contribution

    12 引用 (Scopus)

    抜粋

    A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.

    元の言語English
    ホスト出版物のタイトルProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
    ページ92-93
    ページ数2
    DOI
    出版物ステータスPublished - 2007 12 1
    イベントASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
    継続期間: 2007 1 232007 1 27

    出版物シリーズ

    名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Other

    OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
    Japan
    Yokohama
    期間07/1/2307/1/27

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

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  • これを引用

    Miura, N., & Kuroda, T. (2007). A 1Tb/s 3W inductive-coupling transceiver chip. : Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 92-93). [4196002] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.357798