A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking

Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda

    研究成果: Conference contribution

    14 被引用数 (Scopus)

    抄録

    This paper presents an inductive-coupling interface for NAND Flash memory stacking whose bandwidth per unit area is 2.7Gb/s/mm2 and energy consumption per chip is 0.9pJ/b/chip. The bandwidth is increased by 10x (in other words, layout area is reduced to 1/10 for the same data rate), and the energy consumption is reduced by half, both compared to the latest research results [1]. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in elimination of a source synchronous clock link. As a result, total number of coils needed to form a channel is reduced from 6 to 1, yielding the significant improvement in data rate, layout area and energy consumption.

    本文言語English
    ホスト出版物のタイトル2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
    ページ490-491
    ページ数2
    DOI
    出版ステータスPublished - 2011 5月 12
    イベント2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
    継続期間: 2011 2月 202011 2月 24

    出版物シリーズ

    名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    ISSN(印刷版)0193-6530

    Other

    Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
    国/地域United States
    CitySan Francisco, CA
    Period11/2/2011/2/24

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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