A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme

Takayuki Abe, Yuixiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda

    研究成果: Conference contribution

    10 被引用数 (Scopus)

    抄録

    Short-distance (<10cm) wireless communications applications are rapidly expanding. For instance, a fast file transfer by "touch-and-proceed data communication" provides a user-friendly interface for electronic products [1,2]. Wireless I/O's may replace conventional connectors on a PCB to overcome performance limitations [3,4]. High-speed (>Gb/s), low energy dissipation (<100pJ/b), low bit-error-rate (BER<10 -3), and low cost (small layout area in matured CMOS processes) are required as well as compliance with spectral regulation and EMI/EMS. None of the previous research achievements has satisfied all these requirements (Fig. 26.2.6). Non-coherent UWB transceivers are typically low speed and energy hungry; i.e. 15Mb/s with 2680pJ/b in a heterodyne transceiver [1] and 1Mb/s with 373pJ/b in a direct-conversion transceiver [3]. Millimeter-Wave radio is often used to raise the data rate at the cost of increase in energy dissipation. A heterodyne non-coherent 60GHz transceiver performed 2.5Gb/s with 114pJ/b [2]. To further reduce the energy dissipation a direct-conversion coherent 56GHz transceiver was developed in 40nm CMOS and 11Gb/s was achieved with 6.4pJ/b [4]. Unfortunately, as a free-running TX LO and injection-lock carrier synchronization were employed, the injection locking range was very narrow. For an RF input power of -30dBm, the locking range was 60MHz, only 0.1% of the center frequency. Tight control of frequency under variation and noise is not easy for manufacturing. Raising the RF input power is also limited by the FCC spectral mask regulation. In this paper, we present a UWB direct-conversion coherent transceiver in 90nm CMOS. 2Gb/s with 75pJ/b is achieved while meeting the FCC regulation for indoor communications. An IQ-switching carrier recovery scheme is proposed to save layout area and energy dissipation by 43% and 20%, respectively, compared with those in the conventional Costas loop. The transceiver with the proposed carrier recovery scheme uses binary phase shift keying (BPSK) modulation.

    本文言語English
    ホスト出版物のタイトル2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
    ページ442-443
    ページ数2
    DOI
    出版ステータスPublished - 2012 5 11
    イベント59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
    継続期間: 2012 2 192012 2 23

    出版物シリーズ

    名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    55
    ISSN(印刷版)0193-6530

    Other

    Other59th International Solid-State Circuits Conference, ISSCC 2012
    CountryUnited States
    CitySan Francisco, CA
    Period12/2/1912/2/23

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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