TY - GEN
T1 - A 30Gb/s/link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR
AU - Take, Yasuhiro
AU - Miura, Noriyuki
AU - Kuroda, Tadahiro
PY - 2010/12/1
Y1 - 2010/12/1
N2 - This paper presents a 30Gb/s/link 2.2Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now [1-11]. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, our technique doubles the operation speed and increases the data rate to 30Gb/s/link. As a result, the data rate per layout area is increased to 2.2Tb/s/mm2, which is 2X that of the state-of-the-art inductive-coupling link [1], and 22X that of the state-of-the-art wired link [3].
AB - This paper presents a 30Gb/s/link 2.2Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now [1-11]. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, our technique doubles the operation speed and increases the data rate to 30Gb/s/link. As a result, the data rate per layout area is increased to 2.2Tb/s/mm2, which is 2X that of the state-of-the-art inductive-coupling link [1], and 22X that of the state-of-the-art wired link [3].
UR - http://www.scopus.com/inward/record.url?scp=79952841629&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79952841629&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2010.5716562
DO - 10.1109/ASSCC.2010.5716562
M3 - Conference contribution
AN - SCOPUS:79952841629
SN - 9781424482979
T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
SP - 81
EP - 84
BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Y2 - 8 November 2010 through 10 November 2010
ER -