A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package

Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.

    本文言語English
    ホスト出版物のタイトル2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
    出版社Institute of Electrical and Electronics Engineers Inc.
    ISBN(印刷版)9781479933273
    DOI
    出版ステータスPublished - 2014 1月 1
    イベント28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
    継続期間: 2014 6月 102014 6月 13

    出版物シリーズ

    名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other28th IEEE Symposium on VLSI Circuits, VLSIC 2014
    国/地域United States
    CityHonolulu, HI
    Period14/6/1014/6/13

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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