A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package

Abdul Raziz Junaidi; Yasuhiro Take; Tadahiro Kuroda

doi:10.1109/VLSIC.2014.6858369

A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package

Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.

本文言語	English
ホスト出版物のタイトル	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（印刷版）	9781479933273
DOI	https://doi.org/10.1109/VLSIC.2014.6858369
出版ステータス	Published - 2014 1月 1
イベント	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States 継続期間: 2014 6月 10 → 2014 6月 13

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
国/地域	United States
City	Honolulu, HI
Period	14/6/10 → 14/6/13

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/VLSIC.2014.6858369

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引用スタイル

Junaidi, A. R., Take, Y., & Kuroda, T. (2014). A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers [6858369] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858369

A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. / Junaidi, Abdul Raziz; Take, Yasuhiro; Kuroda, Tadahiro.

2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858369 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

Junaidi, AR, Take, Y & Kuroda, T 2014, A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858369, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 14/6/10. https://doi.org/10.1109/VLSIC.2014.6858369

Junaidi AR, Take Y, Kuroda T. A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858369. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2014.6858369

Junaidi, Abdul Raziz ; Take, Yasuhiro ; Kuroda, Tadahiro. / A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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