抄録
A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.
本文言語 | English |
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論文番号 | 4381457 |
ページ(範囲) | 2726-2735 |
ページ数 | 10 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 42 |
号 | 12 |
DOI | |
出版ステータス | Published - 2007 12月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学