A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker

doi:10.1109/JSSC.2007.908714

A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

研究成果: Article › 査読

20 被引用数 (Scopus)

抄録

A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

本文言語	English
論文番号	4381457
ページ（範囲）	2726-2735
ページ数	10
ジャーナル	IEEE Journal of Solid-State Circuits
巻	42
号	12
DOI	https://doi.org/10.1109/JSSC.2007.908714
出版ステータス	Published - 2007 12

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.2007.908714

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title = "A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX",

abstract = "A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.",

keywords = "CML, CMOS, Clock and data recovery (CDR), Delay line, Demultiplexer, Distributed VCO, Distributed circuits, Hybrid CDR, Jitter tolerance, Optical communications, Oversam-pling, Serializer-deserializer",

author = "Nikola Nedovic and Nestoras Tzartzanis and Hirotaka Tamura and Rotella, {Francis M.} and Magnus Wiklund and Yuma Mizutani and Yusuke Okaniwa and Tadahiro Kuroda and Junji Ogawa and Walker, {William W.}",

year = "2007",

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doi = "10.1109/JSSC.2007.908714",

language = "English",

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AU - Nedovic, Nikola

AU - Tzartzanis, Nestoras

AU - Tamura, Hirotaka

AU - Rotella, Francis M.

AU - Wiklund, Magnus

AU - Mizutani, Yuma

AU - Okaniwa, Yusuke

AU - Kuroda, Tadahiro

AU - Ogawa, Junji

AU - Walker, William W.

PY - 2007/12

Y1 - 2007/12

N2 - A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

AB - A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

KW - CML

KW - CMOS

KW - Clock and data recovery (CDR)

KW - Delay line

KW - Demultiplexer

KW - Distributed VCO

KW - Distributed circuits

KW - Hybrid CDR

KW - Jitter tolerance

KW - Optical communications

KW - Oversam-pling

KW - Serializer-deserializer

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JO - IEEE Journal of Solid-State Circuits

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A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

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