A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

研究成果: Article査読

37 被引用数 (Scopus)

抄録

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10 -12 by laboratory measurements.

本文言語English
ページ(範囲)1680-1686
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
40
8
DOI
出版ステータスPublished - 2005 8月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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