A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro

    研究成果: Conference contribution

    12 被引用数 (Scopus)

    抄録

    This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.

    本文言語English
    ホスト出版物のタイトルESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
    ページ471-474
    ページ数4
    DOI
    出版ステータスPublished - 2011 12月 12
    イベント37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
    継続期間: 2011 9月 122011 9月 16

    出版物シリーズ

    名前European Solid-State Circuits Conference
    ISSN(印刷版)1930-8833

    Other

    Other37th European Solid-State Circuits Conference, ESSCIRC 2011
    国/地域Finland
    CityHelsinki
    Period11/9/1211/9/16

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

    フィンガープリント

    「A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル