TY - GEN
T1 - A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications
AU - Takeya, Tsutomu
AU - Sunaga, Kazuhisa
AU - Yamaguchi, Koichi
AU - Sugita, Hideyuki
AU - Yoshida, Yoichi
AU - Mizuno, Masayuki
AU - Kuroda, Tadahiro
PY - 2010/12/13
Y1 - 2010/12/13
N2 - We present a 6Gb/s wireline receiver having Frequency Division Multiplexing (FDM) with four frequency sub-channels. Its 6GS/s discrete-time filter consumes less power than a conventional filter which requires the same number of high-speed analog mixers as sub-channels and provides channel filtering of FDM signals that contain four 1.5GSymbol/s data. Improved I/Q-based phase detection using only in-phase amplitude makes possible low-power symbol-rate clock recovery. The FDM receiver fabricated in 90nm CMOS process achieves BER<10-12 over a 25cm low-ε channel, while consuming 250mW from a 1.4V supply.
AB - We present a 6Gb/s wireline receiver having Frequency Division Multiplexing (FDM) with four frequency sub-channels. Its 6GS/s discrete-time filter consumes less power than a conventional filter which requires the same number of high-speed analog mixers as sub-channels and provides channel filtering of FDM signals that contain four 1.5GSymbol/s data. Improved I/Q-based phase detection using only in-phase amplitude makes possible low-power symbol-rate clock recovery. The FDM receiver fabricated in 90nm CMOS process achieves BER<10-12 over a 25cm low-ε channel, while consuming 250mW from a 1.4V supply.
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U2 - 10.1109/CICC.2010.5617600
DO - 10.1109/CICC.2010.5617600
M3 - Conference contribution
AN - SCOPUS:78649826339
SN - 9781424457588
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - IEEE Custom Integrated Circuits Conference 2010, CICC 2010
T2 - 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Y2 - 19 September 2010 through 22 September 2010
ER -