A 9-bit 100MS/s SAR ADC with digitally assisted background calibration

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

    研究成果: Article査読

    2 被引用数 (Scopus)

    抄録

    The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1 ×0.13mm2.

    本文言語English
    ページ(範囲)1026-1034
    ページ数9
    ジャーナルIEICE Transactions on Electronics
    E95-C
    6
    DOI
    出版ステータスPublished - 2012 6月

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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