A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.

    本文言語English
    ホスト出版物のタイトル2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
    DOI
    出版ステータスPublished - 2012
    イベント2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan, Province of China
    継続期間: 2012 4 232012 4 25

    出版物シリーズ

    名前2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

    Other

    Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
    国/地域Taiwan, Province of China
    CityHsinchu
    Period12/4/2312/4/25

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ

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