A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/VLSI-DAT.2012.6212592

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm ².

本文言語	English
ホスト出版物のタイトル	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOI	https://doi.org/10.1109/VLSI-DAT.2012.6212592
出版ステータス	Published - 2012
イベント	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan, Province of China 継続期間: 2012 4月 23 → 2012 4月 25

出版物シリーズ

名前	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
国/地域	Taiwan, Province of China
City	Hsinchu
Period	12/4/23 → 12/4/25

ASJC Scopus subject areas

ハードウェアとアーキテクチャ

文献へのアクセス

10.1109/VLSI-DAT.2012.6212592

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引用スタイル

Zhu, X., Chen, Y., Tsukamoto, S., & Kuroda, T. (2012). A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212592] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212592

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. / Zhu, Xiaolei; Chen, Yanfei; Tsukamoto, Sanroku その他.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

研究成果: Conference contribution

Zhu, X, Chen, Y, Tsukamoto, S & Kuroda, T 2012, A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212592, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, Province of China, 12/4/23. https://doi.org/10.1109/VLSI-DAT.2012.6212592

Zhu X, Chen Y, Tsukamoto S, Kuroda T. A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212592

Zhu, Xiaolei ; Chen, Yanfei ; Tsukamoto, Sanroku その他. / A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

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abstract = "The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.",

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A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

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