A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

    研究成果: Conference contribution

    45 被引用数 (Scopus)

    抄録

    A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

    本文言語English
    ホスト出版物のタイトルProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
    ページ145-148
    ページ数4
    DOI
    出版ステータスPublished - 2009 12 1
    イベント2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China
    継続期間: 2009 11 162009 11 18

    出版物シリーズ

    名前Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

    Conference

    Conference2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
    CountryTaiwan, Province of China
    CityTaipei
    Period09/11/1609/11/18

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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