A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (VTH) of the transistors is reduced for high performance at low power-supply voltage (VDD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in VTH, and keeps the VTH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-kb SRAM with 256 rows in fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme.
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