A Case for Low-Latency Network-on-Chip using Compression Routers

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

研究成果: Conference contribution

抄録

The communication latency is a primary concern for designing Network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication latency, we propose an on-chip router that (de)compresses the contents of an incoming packet before completing switch arbitration. The compression router thus has no latency penalty for the compression operation, whereas it shortens a packet length that decreases the network injection-and-ejection latency. Evaluation results show that the compression router improves 7.7% of the parallel application performance (IS, CG, FT, and TSP) and 49% of the effective network throughput by 1.8 compression ratio on NoC. The drawback is that the router area and its energy consumption per bit increase by 0.12mm2 and 1.4 times compared to the conventional virtual-channel router.

本文言語English
ホスト出版物のタイトルProceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021
出版社Institute of Electrical and Electronics Engineers Inc.
ページ134-142
ページ数9
ISBN(電子版)9781665414555
DOI
出版ステータスPublished - 2021 3
イベント29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021 - Virtual, Valladolid, Spain
継続期間: 2021 3 102021 3 12

出版物シリーズ

名前Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021

Conference

Conference29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021
国/地域Spain
CityVirtual, Valladolid
Period21/3/1021/3/12

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 情報システム

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