A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova

研究成果: Conference contribution

97 被引用数 (Scopus)

抄録

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance Computing (HPC) systems can exploit low-latency topologies of high-radix switches. In this context, we propose the use of random shortcut topologies, which are generated by augmenting classical topologies with random links. Using graph analysis we find that these topologies, when compared to non-random topologies of the same degree, lead to drastically reduced diameter and average shortest path length. The best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches. Using flit-level discrete event simulation we find that random shortcut topologies achieve throughput comparable to and latency lower than that of existing non-random topologies such as hypercubes and tori. Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.

本文言語English
ホスト出版物のタイトル2012 39th Annual International Symposium on Computer Architecture, ISCA 2012
ページ177-188
ページ数12
DOI
出版ステータスPublished - 2012 8 15
イベント2012 39th Annual International Symposium on Computer Architecture, ISCA 2012 - Portland, OR, United States
継続期間: 2012 6 92012 6 13

出版物シリーズ

名前Proceedings - International Symposium on Computer Architecture
ISSN(印刷版)1063-6897

Other

Other2012 39th Annual International Symposium on Computer Architecture, ISCA 2012
国/地域United States
CityPortland, OR
Period12/6/912/6/13

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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