A circuit division method for high-level synthesis on multi-FPGA systems

Kugami Daiki, Takaaki Miyajima, Hideharu Amano

研究成果: Conference contribution

抄録

High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).

本文言語English
ホスト出版物のタイトルProceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
ページ156-161
ページ数6
DOI
出版ステータスPublished - 2013 8月 19
イベント27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 - Barcelona, Spain
継続期間: 2013 3月 252013 3月 28

出版物シリーズ

名前Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013

Other

Other27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
国/地域Spain
CityBarcelona
Period13/3/2513/3/28

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • コンピュータ サイエンスの応用

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