A coarse grain reconfigurable processor architecture for stream processing engine

Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

This paper proposes a processor architecture for DR-SPE, a dynamic reconfigurable stream processing engine. DR-SPE is special-purpose hardware for stream data processing, which achieves high processing performance by exploiting parallelism in the target query. It also handles query registration and execution order of operations at runtime. Available operations in DR-SPE are the same as those in Streams on Wires. In this paper, DR-SPE is implemented on a FPGA XC6VLX240T-1, and its performance is evaluated. The results of the evaluation show that DR-SPE achieves register modification within 506 μsec when the configuration path is driven at 1 Mbps, which is not achieved by Streams on Wires. DR-SPE also achieves flexibility and can support complicated queries by providing 10×10 operation units tiled onto an FPGA. DR-SPE achieves comparable operation throughput with Streams on Wires at the expense of requiring more LUTs.

本文言語English
ホスト出版物のタイトルProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
ページ490-495
ページ数6
DOI
出版ステータスPublished - 2011 11 9
外部発表はい
イベント21st International Conference on Field Programmable Logic and Applications, FPL 2011 - Chania, Greece
継続期間: 2011 9 52011 9 7

出版物シリーズ

名前Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

Other

Other21st International Conference on Field Programmable Logic and Applications, FPL 2011
国/地域Greece
CityChania
Period11/9/511/9/7

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用

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