A context dependent clock control mechanism for dynamically reconfigurable processors

H. Amano, Y. Hasegawa, S. Abe, K. Ishikawa, S. Tsutsumi, S. Kurotaki, T. Nakamura, T. Nishimura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Dynamically Reconfigurable Processors improve the area-efficiency by executing a task with multiple hardware contexts. The maximum operational frequency is limited with a context which has the largest delay time, and it causes a certain overhead when each context has various delay time. A context dependent dynamic clock control method, which changes the clock so as to fit the current operational context, is proposed for NEC electronics' DRP-1. A clock generator consisting of a preset-able counter associated with the state transition table for controlling the context switching is proposed. Performance evaluation using several applications reveals that the proposed method improves the performance from 10% to 110% with a small increasing of the power consumption.

本文言語English
ホスト出版物のタイトルProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
ページ575-580
ページ数6
DOI
出版ステータスPublished - 2006
イベント2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
継続期間: 2006 8月 282006 8月 30

出版物シリーズ

名前Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
国/地域Spain
CityMadrid
Period06/8/2806/8/30

ASJC Scopus subject areas

  • 計算理論と計算数学
  • 電子工学および電気工学

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