TY - GEN

T1 - A design of one-dimensional Euler equations for fluid dynamics on FPGA

AU - Abu Talip, Mohamad Sofian

AU - Amano, Hideharu

PY - 2011/8/23

Y1 - 2011/8/23

N2 - Modeling, simulation and optimization using computing tools are the core approach nowadays in science complementary to experiment and theory. Computational Fluid Dynamics (CFD) has evolved many years ago to simulate fluid physics by solving Navier-Stokes equations, or its simple variants, Euler equations. However, most problems spend many hours to get solutions even with expensive supercomputers or clusters. The long computation time required for fluid dynamics simulations has lead the industry to look for some alternatives. Field Programmable Gate Arrays (FPGAs) are becoming more and more attractive for high precision scientific computations. FPGA holds the potential to alleviate this situations. It is possible for an FPGA to configure hundreds of multipliers working concurrently. In this paper, the authors explain the design on implementing the one-dimensional Euler equations in hardware. Two designs with single and double floating-point arithmetic are developed in an FPGA. Synthesis results show that a single floating-point arithmetic design is consumed less area and memory usage, also operating at higher frequency. However, double-precision design is crucial for give a better accuracy of the result.

AB - Modeling, simulation and optimization using computing tools are the core approach nowadays in science complementary to experiment and theory. Computational Fluid Dynamics (CFD) has evolved many years ago to simulate fluid physics by solving Navier-Stokes equations, or its simple variants, Euler equations. However, most problems spend many hours to get solutions even with expensive supercomputers or clusters. The long computation time required for fluid dynamics simulations has lead the industry to look for some alternatives. Field Programmable Gate Arrays (FPGAs) are becoming more and more attractive for high precision scientific computations. FPGA holds the potential to alleviate this situations. It is possible for an FPGA to configure hundreds of multipliers working concurrently. In this paper, the authors explain the design on implementing the one-dimensional Euler equations in hardware. Two designs with single and double floating-point arithmetic are developed in an FPGA. Synthesis results show that a single floating-point arithmetic design is consumed less area and memory usage, also operating at higher frequency. However, double-precision design is crucial for give a better accuracy of the result.

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U2 - 10.1109/ISAS.2011.5960942

DO - 10.1109/ISAS.2011.5960942

M3 - Conference contribution

AN - SCOPUS:80051804881

SN - 9781457707179

T3 - Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011

SP - 170

EP - 173

BT - Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011

T2 - 2011 1st International Symposium on Access Spaces, ISAS 2011

Y2 - 17 June 2011 through 19 June 2011

ER -