A dynamic link-width optimization for network-on-chip

Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous NoC optimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time. Index Terms-Network-on-Chip, router architecture, traffic analysis

本文言語English
ホスト出版物のタイトルProceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
ページ106-108
ページ数3
DOI
出版ステータスPublished - 2011 12月 1
イベント1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan
継続期間: 2011 8月 282011 8月 31

出版物シリーズ

名前Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
2

Other

Other1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
国/地域Japan
CityToyama
Period11/8/2811/8/31

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ ネットワークおよび通信

フィンガープリント

「A dynamic link-width optimization for network-on-chip」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル