A dynamic offset control technique for comparator design in scaled CMOS technology

Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda

研究成果: Conference contribution

12 引用 (Scopus)

抄録

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

元の言語English
ホスト出版物のタイトルProceedings of the Custom Integrated Circuits Conference
ページ495-498
ページ数4
DOI
出版物ステータスPublished - 2008
イベントIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
継続期間: 2008 9 212008 9 24

Other

OtherIEEE 2008 Custom Integrated Circuits Conference, CICC 2008
United States
San Jose, CA
期間08/9/2108/9/24

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Electric power utilization
Networks (circuits)
Compensation and Redress

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Zhu, X., Chen, Y., Kibune, M., Tomita, Y., Hamada, T., Tamura, H., ... Kuroda, T. (2008). A dynamic offset control technique for comparator design in scaled CMOS technology. : Proceedings of the Custom Integrated Circuits Conference (pp. 495-498). [4672130] https://doi.org/10.1109/CICC.2008.4672130

A dynamic offset control technique for comparator design in scaled CMOS technology. / Zhu, Xiaolei; Chen, Yanfei; Kibune, Masaya; Tomita, Yasumoto; Hamada, Takayuki; Tamura, Hirotaka; Tsukamoto, Sanroku; Kuroda, Tadahiro.

Proceedings of the Custom Integrated Circuits Conference. 2008. p. 495-498 4672130.

研究成果: Conference contribution

Zhu, X, Chen, Y, Kibune, M, Tomita, Y, Hamada, T, Tamura, H, Tsukamoto, S & Kuroda, T 2008, A dynamic offset control technique for comparator design in scaled CMOS technology. : Proceedings of the Custom Integrated Circuits Conference., 4672130, pp. 495-498, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, San Jose, CA, United States, 08/9/21. https://doi.org/10.1109/CICC.2008.4672130
Zhu X, Chen Y, Kibune M, Tomita Y, Hamada T, Tamura H その他. A dynamic offset control technique for comparator design in scaled CMOS technology. : Proceedings of the Custom Integrated Circuits Conference. 2008. p. 495-498. 4672130 https://doi.org/10.1109/CICC.2008.4672130
Zhu, Xiaolei ; Chen, Yanfei ; Kibune, Masaya ; Tomita, Yasumoto ; Hamada, Takayuki ; Tamura, Hirotaka ; Tsukamoto, Sanroku ; Kuroda, Tadahiro. / A dynamic offset control technique for comparator design in scaled CMOS technology. Proceedings of the Custom Integrated Circuits Conference. 2008. pp. 495-498
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