A dynamic offset control technique for comparator design in scaled CMOS technology

Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda

    研究成果: Article査読

    1 被引用数 (Scopus)

    抄録

    The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25×65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

    本文言語English
    ページ(範囲)2456-2462
    ページ数7
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E93-A
    12
    DOI
    出版ステータスPublished - 2010 12

    ASJC Scopus subject areas

    • 信号処理
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 電子工学および電気工学
    • 応用数学

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