This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 μm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 μW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of - 80 dBm has been achieved and the transmitter can deliver up to 4 dBm.
|ジャーナル||IEICE Transactions on Electronics|
|出版ステータス||Published - 2004 4|
ASJC Scopus subject areas