A high speed license plate recognition system on an FPGA

Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A pro-totype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-Ill desktop PC. The highest performance in literature; 100 frames per second; can be achieved.

本文言語English
ホスト出版物のタイトルProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
ページ554-557
ページ数4
DOI
出版ステータスPublished - 2007
イベント2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
継続期間: 2007 8 272007 8 29

出版物シリーズ

名前Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
国/地域Netherlands
CityAmsterdam
Period07/8/2707/8/29

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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