A link removal methodology for application-specific networks-on-chip on FPGAs

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Article

抜粋

The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased tra.c generated in some applications makes a customization method for removing links more e.cient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed tra.c information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up */down * routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

元の言語English
ページ(範囲)575-583
ページ数9
ジャーナルIEICE Transactions on Information and Systems
E92-D
発行部数4
DOI
出版物ステータスPublished - 2009 1 1

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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