A link removal methodology for networks-on-chip on reconfigurable systems

Daihan Wang, Hiroki Matsutani, Hideharu Arnano, Michihiro Koibuchi

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

While the regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

本文言語English
ホスト出版物のタイトルProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
ページ269-274
ページ数6
DOI
出版ステータスPublished - 2008 11 3
イベント2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
継続期間: 2008 9 82008 9 10

出版物シリーズ

名前Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
CountryGermany
CityHeidelberg
Period08/9/808/9/10

ASJC Scopus subject areas

  • Hardware and Architecture

フィンガープリント 「A link removal methodology for networks-on-chip on reconfigurable systems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル