A low-power fault-tolerant noc using error correction and detection codes

Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

抄録

Power consumption and reliability become two crucial factors in designing Network-on-Chip (NoC) for modern chip multiprocessors. In this paper, we present a lowpower fault-tolerant NoC architecture by using error correction and detection codes in order to reduce the supply voltage, while the bit error rate of the end-to-end on-chip communication is maintained. The method aims to optimize the power consumption of a given NoC by selecting the best fault-tolerant technique. Simulation results show that our error detection/correction techniques greatly reduce the number of re-transmitted packets due to soft errors. These techniques also reduce up to 40% of flit transmission energy compared to the original NoC without any fault-tolerant techniques. We show that control information of each packet (e.g., destination address) should be protected first by using a high-reliable error detection or correction technique when the error rate is high.

本文言語English
ホスト出版物のタイトルProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
出版社Acta Press
ページ111-118
ページ数8
ISBN(印刷版)9780889868205
DOI
出版ステータスPublished - 2010 1月 1
イベント9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
継続期間: 2010 2月 162010 2月 18

出版物シリーズ

名前Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
国/地域Austria
CityInnsbruck
Period10/2/1610/2/18

ASJC Scopus subject areas

  • 計算理論と計算数学
  • コンピュータ ネットワークおよび通信
  • ソフトウェア

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