A low power NoC router using the marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

研究成果: Conference contribution

抄録

We have concluded that with a router using MMTH the power consumption is associated with the bit change rate of the data, and when NAS parallel benchmarks work on NoC, it is reduced by 42.4% on average at 2GHz compared with a traditional FIFO implementation. The performance degradation caused by the delay of the reading time can be mostly saved by the look-ahead technique in the router.

本文言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII
出版社IEEE Computer Society
ISBN(印刷版)9781479938094
DOI
出版ステータスPublished - 2014
イベント17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 - Yokohama, Japan
継続期間: 2014 4月 142014 4月 16

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII

Other

Other17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014
国/地域Japan
CityYokohama
Period14/4/1414/4/16

ASJC Scopus subject areas

  • 電子工学および電気工学

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