A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Alexis Gryta, Takuma Suguro, Hiroki Ishikuro

研究成果: Conference contribution

1 引用 (Scopus)

抄録

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

元の言語English
ホスト出版物のタイトル2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
出版者Institute of Electrical and Electronics Engineers Inc.
ページ275-278
ページ数4
ISBN(電子版)9781509018307
DOI
出版物ステータスPublished - 2016 12 15
イベント2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
継続期間: 2016 8 32016 8 5

Other

Other2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Hong Kong
Hong Kong
期間16/8/316/8/5

Fingerprint

Modulators
Clocks
Circuit simulation
Schematic diagrams
Scalability
Electric power utilization
Bandwidth
Monitoring

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

これを引用

Gryta, A., Suguro, T., & Ishikuro, H. (2016). A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. : 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 (pp. 275-278). [7785261] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2016.7785261

A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. / Gryta, Alexis; Suguro, Takuma; Ishikuro, Hiroki.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 275-278 7785261.

研究成果: Conference contribution

Gryta, A, Suguro, T & Ishikuro, H 2016, A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. : 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016., 7785261, Institute of Electrical and Electronics Engineers Inc., pp. 275-278, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, Hong Kong, Hong Kong, 16/8/3. https://doi.org/10.1109/EDSSC.2016.7785261
Gryta A, Suguro T, Ishikuro H. A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. : 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 275-278. 7785261 https://doi.org/10.1109/EDSSC.2016.7785261
Gryta, Alexis ; Suguro, Takuma ; Ishikuro, Hiroki. / A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 275-278
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