A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Alexis Gryta, Takuma Suguro, Hiroki Ishikuro

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

    本文言語English
    ホスト出版物のタイトル2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ275-278
    ページ数4
    ISBN(電子版)9781509018307
    DOI
    出版ステータスPublished - 2016 12 15
    イベント2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
    継続期間: 2016 8 32016 8 5

    Other

    Other2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
    国/地域Hong Kong
    CityHong Kong
    Period16/8/316/8/5

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ

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