TY - GEN
T1 - A Method of Partitioning Convolutional Layer to Multiple FPGAs
AU - Iizuka, Kensuke
AU - Ito, Kohei
AU - Hironaka, Kazuei
AU - Amano, Hideharu
N1 - Funding Information:
This work was supported by JST, CREST, innovative computing technology supporting Society5.0, “Development multi-node integrated system for MEC” (JPMJCR19K1) and Keio University Doctoral Student Grant-in-Aid Program.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - We propose a partition method to improve the performance of convolutional neural networks (CNN) on a multi-FPGA system called Flow-in-Cloud (FiC) and implement the 2nd layer of AlexNet on FiC. As a result, our implementation is slightly more energy-efficient than the CPU and the GPU with an optimized machine learning framework.
AB - We propose a partition method to improve the performance of convolutional neural networks (CNN) on a multi-FPGA system called Flow-in-Cloud (FiC) and implement the 2nd layer of AlexNet on FiC. As a result, our implementation is slightly more energy-efficient than the CPU and the GPU with an optimized machine learning framework.
KW - Convolutional Neural Network Accelerators
KW - Deep Learning
KW - Multi-FPGA system
UR - http://www.scopus.com/inward/record.url?scp=85100766532&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85100766532&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9332929
DO - 10.1109/ISOCC50952.2020.9332929
M3 - Conference contribution
AN - SCOPUS:85100766532
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 25
EP - 26
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -