A Method of Partitioning Convolutional Layer to Multiple FPGAs

Kensuke Iizuka; Kohei Ito; Kazuei Hironaka; Hideharu Amano

doi:10.1109/ISOCC50952.2020.9332929

A Method of Partitioning Convolutional Layer to Multiple FPGAs

Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano

情報工学科

研究成果: Conference contribution

抄録

We propose a partition method to improve the performance of convolutional neural networks (CNN) on a multi-FPGA system called Flow-in-Cloud (FiC) and implement the 2nd layer of AlexNet on FiC. As a result, our implementation is slightly more energy-efficient than the CPU and the GPU with an optimized machine learning framework.

本文言語	English
ホスト出版物のタイトル	Proceedings - International SoC Design Conference, ISOCC 2020
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	25-26
ページ数	2
ISBN（電子版）	9781728183312
DOI	https://doi.org/10.1109/ISOCC50952.2020.9332929
出版ステータス	Published - 2020 10 21
イベント	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of 継続期間: 2020 10 21 → 2020 10 24

出版物シリーズ

名前	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

ASJC Scopus subject areas

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

文献へのアクセス

10.1109/ISOCC50952.2020.9332929

他のファイルとリンク

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引用スタイル

Iizuka, K., Ito, K., Hironaka, K., & Amano, H. (2020). A Method of Partitioning Convolutional Layer to Multiple FPGAs. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 25-26). [9332929] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332929

A Method of Partitioning Convolutional Layer to Multiple FPGAs. / Iizuka, Kensuke; Ito, Kohei; Hironaka, Kazuei; Amano, Hideharu.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 25-26 9332929 (Proceedings - International SoC Design Conference, ISOCC 2020).

研究成果: Conference contribution

Iizuka, K, Ito, K, Hironaka, K & Amano, H 2020, A Method of Partitioning Convolutional Layer to Multiple FPGAs. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332929, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 25-26, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9332929

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