A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Koji Tasyo, Hideharu Amano

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency "zero-copy" communication in multi-tasking environments. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). These implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet.

本文言語English
ホスト出版物のタイトルProceedings - 6th International Conference on Parallel Interconnects, PI 1999
編集者Eugen Schenfeld, Ray Kostuk, Craig Lund, Michael Haney
出版社Institute of Electrical and Electronics Engineers Inc.
ページ5-12
ページ数8
ISBN(電子版)076950440X, 9780769504407
DOI
出版ステータスPublished - 1999
外部発表はい
イベント6th International Conference on Parallel Interconnects, PI 1999 - Anchorage, United States
継続期間: 1999 10 171999 10 19

出版物シリーズ

名前Proceedings - 6th International Conference on Parallel Interconnects, PI 1999

Other

Other6th International Conference on Parallel Interconnects, PI 1999
CountryUnited States
CityAnchorage
Period99/10/1799/10/19

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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