A new design scheme for logic circuits with single electron transistors

Ken Uchida, Kazuya Matsuzawa, Akira Toriumi

    研究成果: Article査読

    41 被引用数 (Scopus)

    抄録

    A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

    本文言語English
    ページ(範囲)4027-4032
    ページ数6
    ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
    38
    7 B
    DOI
    出版ステータスPublished - 1999 7 15

    ASJC Scopus subject areas

    • Engineering(all)
    • Physics and Astronomy(all)

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