A new memory module for memory intensive applications

Noboru Tanabe, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hironori Nakajo, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.

本文言語English
ホスト出版物のタイトルInternational Conference on Parallel Computing in Electrical Engineering
ホスト出版物のサブタイトルWorkshop on System Design Automation, SDA, PARELEC 2004
ページ123-128
ページ数6
出版ステータスPublished - 2004 12月 1
イベントInternational Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004 - Dresden, Germany
継続期間: 2004 9月 72004 9月 10

出版物シリーズ

名前International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Other

OtherInternational Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004
国/地域Germany
CityDresden
Period04/9/704/9/10

ASJC Scopus subject areas

  • 工学(全般)

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