A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

Yousuke Yamamoto, Hiroshi Miyanaga, Yoshiji Kobayashi, Yasukazu Terada, Naoaki Yamanaka

研究成果: Article査読

1 被引用数 (Scopus)

抄録

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin.

本文言語English
ページ(範囲)953-955
ページ数3
ジャーナルIEEE Transactions on Communications
34
9
DOI
出版ステータスPublished - 1986 9
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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