A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2

Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Akifumi Watanabe

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the on-chip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.

本文言語English
ホスト出版物のタイトル2009 International Conference on High Performance Switching and Routing, HPSR 2009
DOI
出版ステータスPublished - 2009
イベント2009 International Conference on High Performance Switching and Routing, HPSR 2009 - Paris, France
継続期間: 2009 6 222009 6 24

出版物シリーズ

名前2009 International Conference on High Performance Switching and Routing, HPSR 2009

Other

Other2009 International Conference on High Performance Switching and Routing, HPSR 2009
CountryFrance
CityParis
Period09/6/2209/6/24

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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