A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi, Takeshi Matsubara, Satoshi Kumaki, Abul Hasan Johari, Hiroki Ishikuro, Tadahiro Kuroda

    研究成果: Conference contribution

    4 引用 (Scopus)

    抜粋

    A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

    元の言語English
    ホスト出版物のタイトル2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
    ページ225-228
    ページ数4
    DOI
    出版物ステータスPublished - 2010 12 1
    イベント2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
    継続期間: 2010 11 82010 11 10

    出版物シリーズ

    名前2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

    Other

    Other2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
    China
    Beijing
    期間10/11/810/11/10

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    フィンガープリント A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Hayashi, I., Matsubara, T., Kumaki, S., Johari, A. H., Ishikuro, H., & Kuroda, T. (2010). A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. : 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 225-228). [5716596] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716596