抄録
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including twosurface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.
本文言語 | English |
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ページ(範囲) | 1914-1922 |
ページ数 | 9 |
ジャーナル | IEICE Transactions on Information and Systems |
巻 | E90-D |
号 | 12 |
DOI | |
出版ステータス | Published - 2007 12月 |
ASJC Scopus subject areas
- ソフトウェア
- ハードウェアとアーキテクチャ
- コンピュータ ビジョンおよびパターン認識
- 電子工学および電気工学
- 人工知能