A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, Tadahiro Kuroda

研究成果: Conference contribution

15 被引用数 (Scopus)

抄録

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

本文言語English
ホスト出版物のタイトル2009 Symposium on VLSI Circuits
ページ94-95
ページ数2
出版ステータスPublished - 2009 11 18
イベント2009 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2009 6 162009 6 18

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
国/地域Japan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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