A study on snoop cache systems for single-chip multiprocessors

Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano

研究成果: Article査読

抄録

Progress in device design and implementation technologies will change the structure of bus-connected multiprocessors and allow them to be implemented on a single chip. In such an implementation, the speed of the bus inside the chip is far faster than that of the backplane bus, and data transfer between the chip and external devices will become a bottleneck. Many studies on snoop cache protocols have been made, but they generally assume that the cache memory is on a printed circuit board. In this paper, we first classify the snoop cache protocols in terms of accesses to off-chip shared memory, which will be the principal cause of performance degradation, and then compare them quantitatively. Evaluations are made with an instruction-level multiprocessor simulator and practical parallel applications, varying the cache size or the access latency of shared memory. The results show that an I/N/C protocol that actively uses the line transfers between caches achieves the highest performance under all conditions.

本文言語English
ページ(範囲)62-72
ページ数11
ジャーナルSystems and Computers in Japan
28
2
DOI
出版ステータスPublished - 1998 2月

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • 情報システム
  • ハードウェアとアーキテクチャ
  • 計算理論と計算数学

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