TY - JOUR
T1 - A survey on dynamically reconfigurable processors
AU - Amano, Hideharu
PY - 2006/12
Y1 - 2006/12
N2 - Dynamically reconfigurable processors are consisting of an array of processing elements whose functions and interconnections can be dynamically changed. 9 commercial systems are picked up, and their array structures, processing elements and interconnection architectures are classified.
AB - Dynamically reconfigurable processors are consisting of an array of processing elements whose functions and interconnections can be dynamically changed. 9 commercial systems are picked up, and their array structures, processing elements and interconnection architectures are classified.
KW - Dynamically reconfigurable processors
UR - http://www.scopus.com/inward/record.url?scp=33845573958&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33845573958&partnerID=8YFLogxK
U2 - 10.1093/ietcom/e89-b.12.3179
DO - 10.1093/ietcom/e89-b.12.3179
M3 - Review article
AN - SCOPUS:33845573958
SN - 0916-8516
VL - E89-B
SP - 3179
EP - 3187
JO - IEICE Transactions on Communications
JF - IEICE Transactions on Communications
IS - 12
ER -