A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Hayate Okuhara, Ryosuke Kazami, Hideharu Amano

研究成果: Conference contribution

抄録

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

本文言語English
ホスト出版物のタイトルProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ32-37
ページ数6
ISBN(電子版)9781728148823
DOI
出版ステータスPublished - 2019 10月
イベント13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 - Singapore, Singapore
継続期間: 2019 10月 12019 10月 4

出版物シリーズ

名前Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

Conference

Conference13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
国/地域Singapore
CitySingapore
Period19/10/119/10/4

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 制御と最適化

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