A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology, it does not affect the design of the other layers, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the non-temporal correlation algorithm suffers from 30% performance loss.

本文言語English
ホスト出版物のタイトルProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
ページ383-388
ページ数6
DOI
出版ステータスPublished - 2007
イベント2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
継続期間: 2007 8月 272007 8月 29

出版物シリーズ

名前Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
国/地域Netherlands
CityAmsterdam
Period07/8/2707/8/29

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

フィンガープリント

「A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル